I’m looking for anyone who might know how the 40 SATA lanes from the 8 port multiplier chips on the Rocket 750 are allocated to the 10 SFF-8087 connectors, and figured this forum is my best bet for info. I can’t seem to find a block diagram or a technical doc describing which ports are connected to which chips, and AI isn’t being helpful (rather the opposite).
Intuition and logic suggest that PM1 has 4 lanes to Port1 and 1 lane to Port2, PM2 has 3 lanes to Port2 and 2 to Port3, etc. AI is telling me that the 5th lane on each chip goes to Port9 and Port10, which, from a signal integrity and board layout perspective, is kinda nuts.
Does anyone have any concrete info on how the PMs are mapped to the ports? And more specifically which SATA connectors on the breakout cable, although I’m aware I’ll likely have to test continuity per cable and label them individually. But just ‘side or port 2 closest to port 1’ would be super helpful.
My situation: random read heavy workload with occasional large sequential writes. I want to use 2.5 inch SATA SSDs for this, and they’ll be housed in IcyDock 8-bay Expresscages (MB038SP-B if it matters). I’ll be setting up 5-drive parity arrays (eventually 9-drive but with the 9th drive on a port on the motherboard), and would like to ensure that the 5 drives on any given array are on 5 different PM chips to give me the best speed on those big sequential writes.
On a side note, aside from losing bandwidth, are there any issues with running an R750 in an x4 PCI slot instead of x8?
Thanks in advance!